1. Field of the Invention
The present invention relates to the field of methods of manipulating data, and specifically to computer programs useful for the manipulation and analysis of data strings associated with one or more digital processors or peripheral devices, such as during processor debug analysis.
2. Description of Related Technology
RISC (or reduced instruction set computer) processors are well known in the computing arts. RISC processors generally have the fundamental characteristic of utilizing a substantially reduced instruction set as compared to non-RISC (commonly known as “CISC”) processors. Typically, RISC processor machine instructions are not all micro-coded, but rather may be executed immediately without decoding, thereby affording significant economies in terms of processing speed. This “streamlined” instruction handling capability furthermore allows greater simplicity in the design of the processor (as compared to non-RISC devices), thereby allowing smaller silicon and reduced cost of fabrication.
RISC processors are also typically characterized by (i) load/store memory architecture (i.e., only the load and store instructions have access to memory; other instructions operate via internal registers within the processor); (ii) unity of processor and compiler; and (iii) pipelining.
In addition to the single RISC processor core described above, such cores may be used in conjunction with the same or other types of processor cores, whether as physically discrete components or as functions within a single die. For example, a plurality of similar or identical microprocessor cores may be used to form a multi-processor architecture adapted for parallel processing of data streams. Alternatively, a microprocessor core may be used with a digital signal processor (DSP) core on the same die, the DSP core performing high sampling rate operations requiring its unique architecture (such as FFT calculations or speech processing).
In such multi-core environments (and in fact in other types of configurations), situations frequently arise wherein data may need to be converted from one format to another, or patterns within the data recognized and analyzed to identify useful functional relationships based thereon, or identify problems within the cores. For example, the comparison of the respective processor core stack traces for a debugging program has significant utility for such data manipulation and analysis. Similarly, the designer/programmer may wish to examine state information from the various cores during programming or design synthesis.
One example of the foregoing problem is graphically illustrated in Table 1 below:
TABLE 1Input 1Input 2Input 3Input 4AAASRCCTBBBUCCVDDDBBBGiven the four input strings (i.e., Inputs 1–4) of Table 1, it might be desired to have the output formatted as follows:    [1–3] A    [1] R    [2,3] C    [1–3] B    [1,2] C    [1–3] D    [1–3] B    [4] S    [4] T    [4] U    [4] VHeretofore, algorithms adapted to format or analyze data have not been adapted and optimized for formatting such data derived from a plurality of inputs (such as a plurality of processor cores), and analyzing and recognizing patterns therein, especially in the context of multiprocessor core debug. For example, prior art UNIX-based systems having routines adapted for differencing two files (e.g., “diff”) are generally useful only for comparing two files, and are not optimized for formatting or recognizing patterns or differences within “N” data inputs or files.
When such formatting and analysis of the N inputs is optimized, the analysis/debug process is made more efficient as a whole, and more useful information can be readily extracted. Such is the case in debugging multiple parallel processor cores, such as the aforementioned RISC processors. Consider the example of a debugger, wherein the same program is run on two different processor cores simultaneously, and where the output of both programs is expected to be the same:
SC>go Try                [1] queens.c!26: void Try(Integer I, Boolean *Q) {        [1] Execution stopped at breakpoint.        [2] queens.c!26: void Try(Integer I, Boolean *Q) {        [2] Execution stopped at breakpoint.        SC>source        [1] >26 void Try(Integer I, Boolean *Q) {        [1] 27 Integer J=0;        [1] 28 do {        [1] 29 J++; *Q=False;        [2] >26 void Try(Integer I, Boolean *Q) {        [2] 27 Integer J=0;        [2] 28 do {        [2] 29 J++; *Q=False;        
Note that the output of both processors (identified as “[1]” and “[2]” in the code above) must be visually inspected by the programmer to ensure that the two programs have arrived at the same function together.
Furthermore, in the case where such formatting or pattern recognition is required in a repetitive or iterative fashion, inefficiencies such as the foregoing visual inspection requirement may be multiplied many times over.
Based on the foregoing, there is a need for an improved method and apparatus for formatting such data from a plurality of outputs from one or more threads, and analyzing and recognizing patterns therein. Ideally, such method and apparatus would be adapted to format/analyze a plurality (“N”) of different input sources, confirm the presence of similarities in the data associated with each source, and automatically identify the presence and location of differences therein. Such improved method would also be able to be reduced to an algorithmic or computer program representation for ready use in a variety of different hardware environments.